The present invention relates generally to the design of integrated circuits and, more specifically, to software tools for sizing various elements of an integrated circuit design. Still more specifically, the present invention provides techniques for generating an appropriate number of leaf cell subtypes in a hierarchical design to achieve a particular set of design goals.
The problem of transistor sizing in an integrated circuit design may be stated as follows: given an initial circuit and floor planning (i.e., geometry) information, generate an improved circuit by changing transistor widths such that the improved circuit meets delay constraints, and minimizes objective functions, e.g., energy dissipation or area. Generally speaking, the optimal layout for a particular circuit design would result from an approach in which every transistor is allowed to size independently. However, such an approach would result in too many cells that would have to be laid out. On the other hand, allowing too few cell types or primitives from which to create such a circuit design makes it difficult to meet the delay constraints and to minimize the objective functions.
It is therefore desirable to provide tools for use in the design of integrated circuits which address these issues and strike the appropriate balance for a given application.